1. Field of the Invention
The present invention relates to very large scale integration (“VLSI”) circuits and, more particularly, to reducing cross-talk noise in VLSI circuits.
2. Description of the Related Arts
Conventionally, an integrated circuit chip is comprised of a thin, flat semiconductor substrate having a predefined shape (e.g., rectangular or square) and size (e.g., about 10 millimeters (“mm”) to 25 mm on a side). Integrated into one surface of that substrate are a huge number of microscopic transistors. On top of those transistors are several patterned layers of conductive material and several patterned layers of insulating material that are fabricated in a stack. These insulating layers and conductive layers alternate such that an insulating layer separates any two conductive layers.
All of the conductive layers are patterned to form signal lines that interconnect the transistors, and they are also patterned to form DC voltage busses and ground busses by which power is supplied to the transistors. Some of the signal lines interconnect the transistors into multiple logic gates, for example logic AND gates, OR gates, NAND gates, and the like. The remaining signal lines interconnect the logic gates to each other so that they may perform some predetermined logic function.
With present day technology, the typical number of transistors on a single chip is rapidly approaching one billion. Moreover, the number of logic gates that are formed by the transistors is reaching one million, combinations of which are interconnected through appropriate signal lines. Each such interconnection from the output from one logic gate (the driver) to the input of one or more other logic gates (the receivers) is herein called a “net.”
Ideally, the digital signals which are generated by a driver logic gate on one particular net will not affect the digital signals which are generated by any other driver logic gate on any other net. However, whenever two nets have signal line segments that lie next to each other, then a distributed parasitic capacitance will exist between them; and consequently, a voltage transition on one signal line. This is often referred to as an aggressor net and it will cause a certain amount of cross-talk noise (e.g., noise voltage) to be coupled into the other signal line, which is often referred to as a victim net.
As minimum feature size in circuits is shrinking, signal integrity issues gain importance due to increased coupling between nets in VLSI circuits. This coupling that may result in cross-talk noise (i.e, where the signal on one net (the victim net), is affected by the changes in the signal of its neighboring nets (the aggressor nets)) that can cause functional errors or increase power usage due to spurious switching on victim nets, even though false values are not latched at registers. Decreasing feature sizes affects the cross-talk noise problem in two ways. First, it increases coupling capacitance between nets. Second, smaller transistors cause faster slew rates.
Cross-talk noise depends on the amount of coupling capacitance between a victim net and its neighboring nets versus the victim net's capacitance to ground, aggressor net slew rates, and victim net resistance path to power or ground supply. As coupling capacitance to ground capacitance ratio increases, cross-talk noise increases. Similarly, as aggressor slew rates get faster, cross-talk noise increases. Decreasing victim resistance to power or ground supply will decrease cross-talk noise.
To resolve cross-talk glitch problems, currently different methods are used. Buffering victim nets decreases resistance along discharge path to reduce noise height as well as increasing pin capacitance, which adds capacitance to ground. But this may also make a victim an aggressor, making convergence difficult. Spacing wires apart decreases coupling capacitance, and in effect reduces noise height. However, the effectiveness of this technique is limited in congested designs where introducing extra spacing between wires is not possible.
Therefore, there is a need for a solution to reduce cross-talk noise in VLSI circuits, while limiting or avoiding disturbance of overall circuit design, while minimizing a number of wires touched and allowing or guaranteeing convergence.